1. Field of the Invention
The present invention relates to semiconductor devices and manufacturing methods thereof, and particularly to a semiconductor device having a plurality of circuit parts with different structures, like a memory cell part and logic circuitry, mixed on one substrate, and a manufacturing method thereof.
2. Description of the Background Art
With the improvements toward higher integration and larger capacities in semiconductor devices, particularly in dynamic RAMs (DRAMs), three-dimensionalization of the memory cells have been studied after the 4M (Mega) DRAM generation for the purposes of maintaining soft-error resistance and securing capacitances of the capacitors. The structures for three-dimensional memory cells have been selected as the DRAM generation advances, and they are now being converged into stacked capacitor cells and trench capacitor cells.
In contrast with the trench capacitor cells in which a trench is formed in a silicon substrate to ensure the capacitances; of capacitors with the depth, capacitors are stacked on a silicon substrate in the stacked capacitor cells to ensure the capacitances of the capacitors with the height. Typical stacked capacitor cells include the thick-film stacked capacitor cells which have been used from the 16M DRAM generation, the cylindrical capacitor cells which have been used from the 64M DRAM generation, the Fin capacitor cells, the thick-film rough-surface capacitor cells, etc. Among these stacked capacitor cells, a structure and a fabrication process of a DRAM 90 having cylindrical capacitor cells will be described referring to FIGS. 37A to 46B.
FIGS. 37A, 38A, 39A, 40A, 41A, 42A, 43A, 44A, 45A and 46A are partial sectional views showing the memory cell part of the DRAM 90 and FIGS. 37B, 38B, 39B, 40B, 41B, 42B, 43B, 44B, 45B and 46B are partial sectional views showing the peripheral circuit part including sense amplifiers (amps), decoders, etc., formed around the memory cell part in the DRAM 90.
First, in the process step shown in FIGS. 37A and 37B, a field oxide film 2 is selectively formed in a P-type silicon semiconductor substrate 1.
Then P-type impurity ions and N-type impurity ions are selectively implanted by using resist (not shown) as a mask to form a P-type well region 3 in the memory cell part and a P-type well region 3 and an N-type well region 4 in the peripheral circuit part in the P-type silicon semiconductor substrate 1.
Next, a gate oxide film 5 is formed on the P-type well region 3 and the N-type well region 4 in the part where the field oxide film 2 is not formed and gate electrodes 6 are formed selectively on the gate oxide film 5. At this time, word lines 61 are formed on the field oxide film 2 in the same process step as the gate electrodes 6.
Then N-type impurity (As or P) ions are implanted to a low dose (1.times.10.sup.13 to 1.times.10.sup.14 cm.sup.-2) into the P-type well region 3 right under the gate oxide film 5 in the memory cell part by using the gate electrodes 6 as masks to selectively form N-type source/drain regions 71, 72, 73, and N-type source/drain regions 74, 75 are selectively formed in a similar process in the P-type well region 3 right under the gate oxide film 5 in the peripheral circuit part.
Next, in the process step shown in FIGS. 38A and 38B, an oxide film OX1 is formed all over the surface and resist R1 is formed except on the P-type well region 3 in the peripheral circuit part, and the oxide film OX1 is then etched back by using this resist R1 as a mask to form side wall oxide films 10 on both sides of the gate electrode 6 on the P-type well region 3 in the peripheral circuit part.
Subsequently, by using the gate electrode 6 and the side wall oxide films 10 on the P-type well region 3 in the peripheral circuit part and the resist R1 as masks, N-type impurity ions are implanted to a high dose (1.times.10.sup.15 to 4.times.10.sup.15 cm.sup.-2) into the N-type source/drain regions 74 and 75 to form N.sup.+ -type source/drain regions 91 and 92.
Next, after removing the resist R1, in the process step shown in FIGS. 39A and 39B, resist R2 is formed except on the N-type well region 4 in the peripheral circuit part and the oxide film OX1 is etched back by using the resist R2 as a mask to form side wall oxide films 10 on both sides of the gate electrode 6 on the N-type well region 4 in the peripheral circuit part.
Subsequently, by using the gate electrode 6 and the side wall oxide films 10 on the N-type well region 4 in the peripheral circuit part and the resist R2 as masks, P-type impurity (B or BF.sub.2) ions are implanted to a high dose (1.times.10.sup.15 to 4.times.10.sup.15 cm.sup.-2) into the N-type well region 4 to form P.sup.+ -type source/drain regions 81 and 82.
Next, the resist R2 is removed, and then in the process step shown in FIGS. 40A and 40B, an oxide film is formed all over the surface and an interlayer insulating film 11 is formed by planarization. The interlayer insulating film 11 is referred to as an interlayer insulating film underlying bit lines so that it can be distinguished from other interlayer insulating films.
Next, a bit line contact hole 12 is formed through the interlayer insulating film 11 to reach the N-type source/drain region 72 in the memory cell part.
Next, a polysilicon layer, containing N-type impurities, is formed over the entire surface of the interlayer insulating film 11, and then the polysilicon layer is removed by CMP (Chemical Mechanical Polishing) except in the bit line contact hole 12 to form a polysilicon plug 13 in the bit line contact hole 12.
Next, in the process step shown in FIGS. 41A and 41B, bit line contact holes 14 are formed through the interlayer insulating film 11 to reach the N.sup.+ source/drain regions 91 and 92 and the P.sup.+ -type source/drain regions 81 and 82 in the peripheral circuit part. Then a metal layer of TiN (titanium nitride) or W (tungsten), or a multi-layered film thereof, is formed all over the interlayer insulating film 11 and the metal layer is then removed by CMP except in the bit line contact holes 14 to form metal plugs 15 in the bit line contact holes 14.
Next, in the process step shown in FIGS. 42A and 42B, a metal layer of TiN or W, or a multi-layered film thereof, is formed all over the interlayer insulating film 11 and patterned by photolithography and etching to form metal bit lines 16. The metal bit lines 16 are so patterned that they are connected to the polysilicon plug 13 and the metal plugs 15.
Although the metal bit lines 16 in the peripheral circuit part do not always function only as bit lines, they are so named because they are formed in the same process as the bit lines in the memory cell part. Also, the bit line contact holes 14 are so named because they are connected to the metal bit lines 16, though they are not always connected to bit lines.
Although not shown in FIGS. 37B, 38B, 39B, 40B, 41B and 42B, a TG (Transfer Gate) wiring is formed in the peripheral circuit part in the same fabrication process as the word lines 61 (i.e., the gate electrodes 6), for example. Since the TG wiring is formed in almost the same layer as the gate electrodes 6, it may be electrically connected with the metal bit lines 16 by using the bit line contact holes 14.
That is to say, in the process step shown in FIG. 41B, a bit line contact hole (almost the same as the bit line contact holes 14) reaching the TG wiring through the interlayer insulating film 11 may be formed at the same time when forming the bit line contact holes 14, and then a metal plug 15 is buried also in the bit line contact hole reaching the TG wiring at the same time when the metal plugs 15 are buried in the bit line contact holes 14.
Next, in the process step shown in FIGS. 43A and 43B, an oxide film is formed all over the surface of the interlayer insulating film 11 and an interlayer insulating film 17 is formed by planarization. The interlayer insulating film 17 is called an interlayer insulating film underlying storage nodes so that it can be distinguished from other interlayer insulating films.
Next, storage node contact holes 18 are formed through the interlayer insulating films 11 and 17 to reach the N-type source/drain regions 71 and 73 in the memory cell part at least.
Next, when a conductor layer for the formation of storage nodes is formed all over the interlayer insulating film 17 with N.sup.+ polysilicon into which N-type impurities are introduced to a high concentration, for example, the conductor layer for the formation of storage nodes is also buried in the storage node contact holes 18 to form buried layers 31.
Then a thick insulating film is formed all over the surface and then the conductor layer for the formation of storage nodes and the thick insulating film are removed through a process of photolithography and etching, leaving bottom films 19 forming the bottom of the storage nodes and the thick insulating film on the bottom films 19. Now the thick insulating films on the bottom films 19 are called insulating films 26 for the formation of cylindrical capacitors.
Next, in the process step shown in FIGS. 44A and 44B, a conductor layer for the formation of storage nodes is formed again all over the surface and is selectively removed by etch back so that it is left only around the bottom films 19 and insulating films 26 for the formation of cylindrical capacitors. The remaining parts of the conductor layer for the formation of storage nodes form side films 20 serving as side walls of the storage nodes. The bottom films 19 and the side films 20 form storage nodes SN.
Next, only the insulating films 26 for the formation of cylindrical capacitors are removed and a capacitor gate insulating film 21 is formed on the surface of the bottom films 19 and the side films 20 in the process step shown in FIGS. 45A and 45B. Then a conductive film for the formation of cell plate is formed all over the surface and the conductive film for cell plate formation is left only in the memory cell part through a process of photolithography and etching. The remaining conductive film for the formation of cell plate forms a cell plate electrode 22.
Next, in the process step shown in FIGS. 46A and 46B, an oxide film is formed all over the surface and an interlayer insulating film 23 is formed by planarization. The interlayer insulating film 23 is called an interlayer insulating film underlying aluminum wiring so that it can be distinguished from other interlayer insulating films.
Next, an aluminum wiring contact hole 24A reaching the cell plate electrode 22 is formed in the memory cell part and aluminum wiring contact holes 24B reaching the metal bit lines 16 electrically connected to the N.sup.+ -type source/drain region 92 and the P.sup.+ -type source/drain region 81 are formed through the interlayer insulating films 23 and 17 in the peripheral circuit part.
Next, when a conductor layer for the formation of aluminum wiring is formed all over the surface of the interlayer insulating film 23, the conductor layer for the formation of aluminum wiring is also buried in the aluminum wiring contact holes 24A and 24B. At this time, buried layers 32 are formed in the aluminum wiring contact holes 24A and 24B. Although a conductor layer for the formation of aluminum wiring is buried in the aluminum wiring contact holes 24A and 24B in this example, it is not limited to aluminum but may be any conductor layer of metal or the like.
Then, through a process of photolithography and etching, aluminum wiring 25 is formed on the interlayer insulating film 23 in the memory cell part and the peripheral circuit part to obtain a DRAM 90 having cylindrical capacitor cells.
Although not shown in FIGS. 42B, 43B, 44B, 45B and 46B, a BL (Bit Line) wiring is formed in the same fabrication process as the metal bit lines 16 in the peripheral circuit part, for example. Since it is formed in almost the same layer as the bit lines 16, the BL wiring and the aluminum wiring 25 may be electrically connected by using the aluminum wiring contact holes 24B.
Generally, with highly-integrated and large-capacity DRAMs, high resolution is required in photolithography, and therefore the focus margin is reduced as trade off.
Accordingly, if the difference in level at the pattern step becomes larger over the focus margin as the degree of integration increases and the capacity becomes larger, it is then very difficult to form wirings by photolithography. Especially, with stacked capacitor cells which are formed by stacking capacitors on a silicon substrate, the difference in level at the pattern step is noticeable, and it is therefore essential to reduce the step height. The interlayer insulating film 11, the interlayer insulating film 17 and the interlayer insulating film 23 therefore undergo planarization as shown in FIGS. 46A and 46B.
However, such a planarization process tends to cause the problem that the thickness of the interlayer films from the aluminum wiring to the silicon substrate becomes too thick, and then it will be quite difficult to make contact holes for connecting the aluminum wiring and the silicon substrate, or the aluminum wiring and the TG wiring. Accordingly, as shown in FIGS. 46A and 46B, in the peripheral circuit part, the aluminum wiring and the silicon substrate, or the aluminum wiring and the TG wiring, are electrically connected by the metal plugs 15 buried in the bit line contact holes 14 through the metal bit lines 16 and BL wiring (not shown).
However, the use of the metal plugs 15 in the peripheral circuit part may cause such inconveniences as described below.
That is to say, after the bit line contact holes 14 have been made and the metal plugs 15 have been formed, completing the DRAM fabrication process requires the process steps for forming the metal bit lines 16, capacitors (storage nodes) SN, interlayer insulating film 17 underlying the capacitors, interlayer insulating film 23 underlying the aluminum wiring, etc., as has been described referring to FIGS. 42A to 46B.
Thermal processes around 800 to 850.degree. C. for several tens of minutes are required for the formation of the interlayer insulating films 17, 23, sintering of the capacitor gate insulating film 21, and for electric activation of the polysilicon material. These thermal processes considerably increase the contact resistance at the interface between the metal plugs 15 buried in the bit line contact holes 14 in the peripheral circuit part and the silicon substrate, i.e., at the interface with the N.sup.+ -type source/drain regions 91 and 92 and the P.sup.+ -type source/drain regions 81 and 82, and also considerably increase the junction leakage current. For example, as compared with a thermal process at about 400.degree. C. for several tens of minutes, the contact resistance is increased 10 times or more and the junction leakage current is increased 100 times or more. The reason will be considered below.
A thermal process at 800 to 850.degree. C. causes metal atoms constituting the metal plugs 15 to aggregate at the interface between the metal plugs 15 buried in the bit line contact holes 14 and the silicon substrate, which results in formation of voids. It is supposed that the presence of voids reduces the contact area between the metal plugs 15 and the silicon substrate. In electric characteristics, this phenomenon appears as an increase in contact resistance.
It is also supposed that a thermal process at 800 to 850.degree. C. causes metal atoms constituting the metal plugs 15 to diffuse into the silicon substrate at the interface between the metal plugs 15 buried in the bit line contact holes 14 and the silicon substrate to break pn junction in the silicon substrate. In electric characteristics, this phenomenon appears as an increase in junction leakage current. When the metal is aluminum or cobalt, the substrate side is spiked and dented, which is called spike phenomenon.
Further, a thermal process at 800 to 850.degree. C. also causes impurity ions in the diffusion layer, i.e., the N.sup.+ -type source/drain regions 91 and 92 and the P.sup.+ -type source/drain regions 81 and 82, to diffuse into the silicon substrate. Then the impurity ion concentration decreases at the interface between the metal plugs 15 buried in the bit line contact holes 14 and the silicon substrate, i.e., at the interface with the N.sup.+ -type source/drain regions 91 and 92 and the P.sup.+ -type source/drain regions 81 and 82, which results in an increase in contact resistance, too.